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Si532
2
Rev. 1.0
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Voltage1
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
Supply Current
IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
111
99
90
81
121
108
98
88
mA
TriState mode
—
60
70
Output Enable (OE)
and Frequency Select (FS)2
VIH
0.75 x VDD
——
V
VIL
——
0.5
Operating Temperature Range3
TA
–40
—
85
C
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE and FS pins include a 17 k
pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
3. If the device is powered up below –20 C and the ambient temperature rises by approximately 105 C during normal
operation, the device will perform a one-time recalibration. The output is squelched for approximately 2–3 ms during
this recalibration.
Table 2. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Nominal Frequency1,2
fO
LVPECL/LVDS/CML
10
—
945
MHz
CMOS
10
—
160
Initial Accuracy
fi
Measured at +25 °C at
time of shipping
—±1.5
—
ppm
Temperature Stability1,3
f/fO
–20
–50
—
+20
+50
ppm
Aging
fa
Frequency drift over
projected 15 year life
——
±10
ppm
Powerup Time4
tOSC
——
10
ms
Settling Time After FS Change
tFRQ
——
10
ms
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
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